A carrier for integrated circuit devices is typically fabricated of semiconductor, glass, or glass-ceramic material as a freestanding substrate, chip or wafer having conductive through-vias. The through-vias are exposed on the top and underside of the carrier and are insulated from each other. Multiple levels of carrier material with metallic or semi-metallic vias are often required to obtain the necessary conductive paths between chips and other devices mounted with respect to the carrier. The carrier having through-vias provides chip input/output terminals (I/O), with the chips typically mounted in the “flip chip” manner, and other device I/O through the carrier from the surface at which the chip or device is mounted to the other side of the carrier, which may include a next level of packaging, a board, or additional flip-chips mounted on that side of the carrier.
FIG. 1 provides a representative illustration of a carrier in accordance with this invention. Carrier 102 comprises a layer 104 of insulative or semiconductive material, for example silicon, fused silica (“glass”, “quartz”), ceramic, or another semiconductor or insulator. The carrier 102 has multiple through-vias, shown as 105 representatively, which extend from the upper or top surface of the carrier layer 104 to the bottom surface of the carrier layer 104. The through-vias are filled with a metallic or semi-metallic conductive via material, shown as conductor 115, to provide conductive paths through the carrier. Solder bumps, C4s, or the like, shown as 114, are disposed at the bottom surface of carrier layer 104 in electrical contact with the conductive via material 115 in order to join the carrier to a next level. At the upper surface of carrier layer 104, the conductive material 115 in the through-vias may be placed in electrical contact with additional multilevel wiring, integrated circuits or associated devices, optical or optoelectronic elements, microelectromechanical elements, etc. disposed in layers 106 which are, in turn, connected to the chip connectors, shown as microjoints 125, of chip 120. Semiconductor devices may also be embedded in the substrate and electrically incorporated into the aforementioned integrated circuits. Should additional multilevel wiring not be needed, the microjoints of chip 120 can be bonded directly to the conductive via material 115.
Problems have arisen in carriers of the prior art due to limitations in materials, deposition methods, control of dimensional tolerances, and mechanical stresses encountered during processing of the materials. Traditional substrate thicknesses are in the range of 0.5 mm to 20 mm with through-via aspect ratios in the range of 1:1 to 2:1. Through-vias may be tapered or vertical as dictated by the forming technology. For instance, vias formed by a punch technique display a breakout region and laser vias can be tapered depending upon the aspect ratio. Typical pitches may be 225 μm for glass ceramic substrates at the present, and 150 μm for ceramic substrates. Depending upon the desired via density, given the number of chips or other devices to be joined to the carrier and the number of desired bonding sites, the via diameters would accordingly range from 25 to 300 μm.
There is a need to miniaturize such carriers to accommodate single or multiple flip-chips and micro-components with I/O densities of from 1,000 to 10,000 per cm2, with overall physical dimensions being in the single cm range for length and width and in the range of a single μm to a few 100 μms in thickness. For high speed and low power, the through-vias and associated connections must present series resistances lower than several 100 mΩs to several tens of mΩs, or else signal risetimes will be degraded. This in turn specifies that through-vias filled with typical conductive materials be of a height in the range of a single μm to several hundred μms with diameters of several 10's to ˜100 μm.
Filling such high aspect ratio vias is challenging. A popular technique for filling blind vias or through-vias of micro-scale diameters is electroplating of Cu. However, the hydrodynamics, the ionic concentrations, and the diffusivities limit the filling of deep blind holes. Authors Tomisaka et al. (ECTC 2002) did extensive plating optimization and were still not able to eliminate voids in vias of only 70 μm deep. Methods for filling large blind holes which are to be opened later break down or become impractical at such dimensions. The U.S. Pat. No. 5,998,292 of Black, et al details a method for creating insulated conductive through-holes in a semiconductor wafer for 3-dimensional wafer joining. Black's method involves etching so-called blind holes only partially through the semiconductor substrate, insulating the holes' sidewalls, filling the insulated holes with metal selected from tungsten, chromium, copper, aluminum, nickel, indium, gold, and mixtures or alloys thereof, planarizing the top surface and removing excess metal, and then grinding away the bottom semiconductor material to expose the bottom of the filled vias (i.e., to open the blind holes). U.S. Pat. Nos. 5,646,067 and 5,814,889 and 5,618,752 of Gaul use the Black approach applied to a silicon carrier layer with tungsten or polysilicon through vias. Chiu et al. (U.S. Pat. No. 6,593,644) describe a similar process to create a Si-based chip carrier, with through-vias filled by Cu, Ni, or Al. The Black method provides adequate fill of the through-vias (for some of the listed materials); however, given the materials used, the resulting structure will experience the mechanical failures described below with reference to Table 1. Gaul utilizes materials that are more closely thermally matched, namely W and poly-Si, but would not have practical deposition methods for multi-10's of μm and would have vastly differing values for modulus. It is also to be noted that incorporation of embedded components into present carriers is difficult due to processing limitations, such as high temperature sintering conditions for ceramic carriers, as well as limitations with embedded component material systems.
At the above-stated diameters, most metals which are commonly used for integrated circuit interconnect vias generate unacceptable stress levels on the carrier layer material (e.g., Si or glass) due to thermal expansion mismatch. In addition, the metal structures exhibit top surface extrusions, ruptures, or expansions during and after typical thermal cycling. For carrier substrates and integrated devices that are comprised of brittle materials, such as semiconductors, glass, or ceramics, the risk of mechanical failure by brittle fracture is significant given the thermal expansion mismatches and the fragility of the carrier materials. In addition to brittle fracture, interfacial delamination is likely when employing standard materials and combinations of materials at the stated dimensions. Table 1 provides a listing of commonly used materials, namely silicon for substrates, and copper, tungsten, and nickel for the metal, and their mechanical properties.
YOUNG'SPOISSONMATERIALMODULUS (GPa)RATIOCTE (ppm/° C.)Silicon1700.283doped1700.282polysiliconCopper1300.3416.5Tungsten4110.284.5Nickel2000.3113.4
Of the metals commonly used for substrate metallization, only tungsten (W), with a CTE of ˜5 ppm/° C. approaches the CTE of silicon (Si). However, the modulus of W is so high (>400 GPa) compared to that of silicon (˜170 GPa) that brittle fracture of the Si and/or delamination of via sidewalls are likely, given the finite but small thermal expansion mismatch. Like W, the typical processes used to grow or deposit poly-Si are only practical for thicknesses up to ˜1 or several single μm, and often are limited to deposition temperatures above the maximum temperatures that can be tolerated by integrated circuit components or wiring on the substrate above (if these are to be fabricated prior to filling the through-vias).
Three potential problems associated with large CTE mismatches between vias and the Si substrate include delamination at the via sidewalls (resulting in so-called “rattling vias” that exhibit compromised conductivity and mechanical stability), cracking of the Si substrate between vias, and piston-like ruptures of any overlying or underlying structures or thin films in contact with the top and bottom surfaces of the vias. The following reference discusses via cracking issues: “Fiber-End Cracking in Brittle-Matrix Composites: A Model Study”, J. A. Casey, D. R. Clarke and Y. Fu, in Metal-Ceramic Interfaces, Proceedings of an International Workshop, ACTA Met, 1990.
The vertical extrusion due to sidewall stresses is determined by the thermal expansion mismatch, the modulus, and the Poisson ratio. The forces resulting from the extrusion and acting on the overlying or underlying structures or thin films increase with the modulus of the through-vias. The piston-like failures can be avoided by minimizing the thermal expansion mismatch, the Poisson ratio, and the modulus of the through-vias. If a conductive material has a CTE which is exactly the same as that of the substrate materials, then the modulus and Poisson ratio of the conductive material would not be an issue.
What is needed, therefore, and what is an object of the present invention is to provide a carrier structure which can be fabricated at the desired dimensions and which can withstand thermal cycling experienced during production, joining processing, and use.
Another object of the present invention is to provide a through-via structure including conductive material having a coefficient of thermal expansion which closely matches the substrate material, a reduced modulus and a reduced Poisson ratio in order to minimize the negative effects of thermal mismatch.
Yet another object of the present invention is to provide a through-via structure which includes multiple differing materials having different coefficients of thermal expansion, to result in a through-via having an effective coefficient of thermal expansion which most closely matches that of the substrate, to minimize the negative effects of thermal mismatch.
Another object of the invention is to provide a through-via structure which includes multiple differing materials having different coefficients of thermal expansion, to result in a through-via having an effective coefficient of thermal expansion which closely matches that of the substrate material and an effective modulus which most closely matches that of the substrate, or which is reduced to be less than that of the substrate, to reduce mechanical stresses encountered in processing and use.